1. Field of the Invention
The present invention relates to a digital circuit apparatus having the function of adjusting the phase of an internal clock generated by a voltage-controlled oscillator and the phase of an external clock inputted from the outside. More particularly, it relates to a digital circuit apparatus which can reduce the time required to resume the generation of the internal clock that has temporarily been halted.
2. Description of Related Art
By way of example, FIGS. 1 and 2 show the configuration of a digital circuit apparatus having the function of adjusting the phase of an internal clock generated by a voltage-controlled oscillator (hereinafter referred to as VCO circuit) and the phase of an external clock supplied from the outside.
FIG. 1 is a block diagram showing the configuration of a PLL (Phase Locked Loop) composed of the VCO circuit, wherein the external clock supplied from the outside is inputted to one input terminal of a phase comparator 3, and a phase comparison result signal 4 outputted from the phase comparator 3 is inputted to a low-pass filter 5. A VCO-circuit voltage control signal (herein after referred to as VCO voltage control signal) 6 outputted from the low-pass filter 5 is inputted to the VCO circuit 17. The VCO circuit 17 outputs an internal clock 18, which is inputted to a frequency divider 19. A divided frequency clock 2 outputted from the frequency divider 19 is inputted to the other input terminal of the phase comparator 3.
Next, a description will be given to the operation of the digital circuit apparatus. Upon energizing the digital circuit apparatus, the VCO circuit 17 initiates an oscillating operation. The oscillation frequency of the VCO 17 varies as the value of the VCO voltage control signal 6 varies. Here, the digital circuit apparatus is constituted so that the oscillation frequency of the VCO circuit 17 increases as the voltage of the VCO voltage control signal 6 increases. The frequency divider 19 divides the frequency of the internal clock 18 outputted from the VCO circuit 17 at a specified ratio and outputs the divided frequency clock 2. The phase comparator 3 outputs a phase comparison result signal 4 indicating the lead of the divided frequency clock 2 in phase, during the period in which the divided frequency clock 2 is ahead of the external clock 1 in phase. On the other hand, the phase comparator 3 outputs a phase comparison result signal 4 indicating the delay of the divided frequency clock 2 in phase, during the period in which the divided frequency clock 2 is behind the external clock 1 in phase.
When the phase comparison result signal 4 is inputted to the low-pass filter 5, the low-pass filter 5 lowers the VCO voltage control signal 6 during the period in which the phase comparison result signal 4 indicating the lead of the divided frequency clock 2 in phase is inputted, while it raises the VCO voltage control signal 6 during the period in which the phase comparison result signal 4 indicating the delay of the divided frequency clock 2 in phase is inputted. Thus, when the divided frequency clock 2 is behind the external clock 1, the low-pass filter 5 raises the VCO voltage control signal 6 so that the oscillation frequency of the VCO circuit 17 increases, thereby causing the divided frequency clock 2 to be ahead of the external clock 1 in phase. Conversely, when the divided frequency 2 is ahead of the external clock 1, the divided frequency clock 2 is caused to lessen the degree of its lead in phase.
After the time required to match the phases elapsed, the phase and frequency of the divided frequency clock 2 eventually become the same as those of the external clock 1, while the frequency of the internal clock 18 becomes an integral multiple of the frequency of the external clock 1, thereby establishing a predetermined phase relationship. Therefore, the digital circuit apparatus is effective in the case of using the external clock 1 as the internal clock 18 after integrally multiplying its frequency or in the case of requiring the internal clock 18 having substantially no phase difference between the external clock 1 and itself, which is obtained by compensating for the delay of a clock buffer.
Specific examples of the phase comparator 3, the low-pass filter 5, and the VCO circuit 17 are well known. Well-known examples of the phase comparator 3 are shown in: FIG. 3(a) of "Design of PLL-Based Clock Generation Circuits" (IEEE Journal of Solid-State Circuits, Vol.22 No.2, Apr. 1987, pp.255-261) [Document I]; and FIG. 7 of "A Variable Delay Line PLL for CPU-Coprocessor Synchronization" (IEEE Journal of Solid-State Circuits, Vol.23, No.5, Oct. 1988, pp.1218-1223) [Document II]. Well-known examples of the low-pass filter circuit 5 are shown in: FIG. 3(b) of [Document I] mentioned above; and FIG. 8 of [Document II] mentioned above. Well-known examples of the VCO circuit 17 are shown in FIGS. 4(a) and 3(c) of [Document I].
FIG. 2 is a block diagram of a digital circuit apparatus in which the phases of two clocks are synchronized by means of a Voltage Control Delay Line (hereinafter referred to as VCDL) circuit. The external clock 1 is inputted to a first circuit block 23 and a first internal clock 24 is outputted from the first circuit block 23. The first internal clock 24 is inputted to one input terminal of the phase comparator 3 in a second circuit block 25. The external clock 1 is inputted to a VCDL circuit 60 in the second circuit block 25, while a second internal clock 26 is outputted from the VCDL circuit 60. The second internal clock 26 is inputted to the other input terminal of the phase comparator 3. The phase comparison result signal outputted from the phase comparator 3 is inputted to the low-pass filter 5, while a VCDL voltage control signal 61 is supplied to the VCDL circuit 60.
Next, a description will be given to the operation of the digital circuit apparatus. The internal clocks are generated from the external clock 1 in the circuit blocks 23 and 25. When the delay of the internal clock 24 in the first circuit block 23 is significant, the phase difference between the internal clocks 24 and 26 is diminished by delaying the internal clock 26 in the second circuit block 25. As for the portion for generating the VCDL voltage control signal 61 by means of the phase comparator 3 and the low-pass filter 5, it is similar to the portion shown in FIG. 1, and the VCDL voltage control signal 61 outputted from the low-pass filter circuit 5 is inputted to the VCDL circuit 60. Since the external clock 1 has been inputted to the VCDL circuit 60, the phase difference between the external clock 1 anti the internal clock 26 outputted from the second circuit block 25 is adjusted in accordance with the voltage value of the VCDL voltage control signal 61.
When the internal clock 26 outputted from the second circuit block 25 is delayed, the phase difference between the internal clock 26 and the internal clock 24 outputted from the first circuit block 23 is reduced. Consequently, it becomes easier for the second circuit block 25 to sample a signal generated in the first circuit block 23 in synchronization with the internal clock 24.
Examples of the VCDL circuit 60 are shown in FIGS. 5 and 3(b) of [Document II] mentioned above. The VCDL circuit and the VCO circuit can be implemented by similar circuit configurations, except that the input signal to the VCDL circuit is delayed only through a voltage control delay system before it is outputted, while the VCO circuit is constituted so that the output signal from the voltage control delay system is inverted before it is fed back to the input of the VCO circuit.
In the above-mentioned digital circuit apparatus, when the supply of the internal clock is temporarily halted for the purpose of lowering power consumption during the period in which the circuit operation is not needed, the analog output voltage of the low-pass filter constituting the PLL varies during the period in which the internal clock is halted. In the case of resuming the supply of the internal clock afterward, it is necessary to adjust the phases of the clocks again from the beginning. Consequently, in resuming the generation of the internal clock that has temporarily been halted, there is required a period of time for adjusting the phases ranging from several tens of clock cycles to several thousands of clock cycles, similarly to the phase adjustment in initiating the energization of the digital circuit apparatus. Since the external clock and internal clock do not match in phase in the mean time, transmission of a signal can not be resumed between the digital circuit apparatus and the outside.